1. Field of the Invention
The invention in general relates to the use of error correcting codes for binary data with respect to the coding of the data, the detection of errors occurring in the coded data, as well as (if possible) with respect to the correction of such errors. The standard work in this field is the book by Peterson and Weldon: Error Correcting Codes, MIT Press. For understanding the present invention, reference is made notably to chapters 2 and 6 thereof. In particular, the invention relates to a memory having a first memory bank with memory locations, each of which serves for storing one memory word therein and which include a sufficient number of bit locations for the storage of the data bits of a memory word and associated redundancy bits, so that for each memory word at least one detected error bit can be corrected, and furthermore having an input device with an address input, a data line for an addressed data word, and a corrector device which is connected to the data line in order to present, under the control of an incorrect data word read which is received therein, a corrected data word on an output of the corrector device.
2. Description of the Prior Art
Known memories are matrix-organized semiconductor memories, but the present invention is not restricted thereto or even to random access memories. A known error correcting code enables the correction of one error per memory word (SEC). Another known code is capable of correcting one error per memory word and of detecting two errors per memory word (SEC-DED). In accordance with the SEC system, a code word of n bits (data bits+detection/correction bits) should comprise at least log.sub.2 (n+1) redundancy bits. This means that the number of redundant bits is comparatively large for a small word length. The invention has for its object to limit the percentage of redundant bits for each memory word. The invention aims to realise this object by means of user words of limited length, because a user word of long length cannot be processed in a processing device (cpu) and/or because a wide data path is expensive. A user word is a word accessible by means of a memory address available to the user of the data system. The objects in accordance with the invention are achieved in that the data line has connected to it a detector device for a data word read from the memory and a detection output of the detector device being connected to an activation input of the corrector device. Memory locations for the memory words are sub-divided into a fixed number of word locations for user words, each location being separately addressable by a user address signal. Each user word comprises at least one bit location for a redundancy bit, with the result that at least one error bit in said user word can be detected by the detector device. A signal on said detector output is capable, in cooperation with said user address signal, of addressing the other word locations for user words of the same memory word, including their redundancy bits, in order to present the complete memory word thus addressed, including a predetermined number of correction bits added to the relevant memory word and also stored in the memory, to the corrector device in order to activate a correction.
As long as no error is detected, it is sufficient to read the desired, comparatively short user words of, for example, 8 or 16 bits. It is only when an error is detected that the comparatively long memory word is read for the correction of the error. If a user word contains for example, eight data bits, it should contain four correction bits in accordance with the said rule; thus, it has an added redundancy of 50%.